RISC-V

Note

TL;DR - Amarula Solutions’ mainline U-Boot and Linux kernel BSP documentation for this vendor/SoC family — covering build instructions, SD/flash boot procedures, and device tree configuration. - All boards use mainline U-Boot and Linux kernels with the upstream-first methodology.

Contents:

• QEMU RISC-V
  • Testing RISC V under qemu
• SiFive
  • HiFive Unleashed A00

Tip

Need BSP support for RISC-V platforms? Amarula Solutions provides U-Boot, OpenSBI, and Linux kernel mainlining with Yocto/Buildroot integration for SiFive and other RISC-V hardware. Contact our BSP team